Testing integrated circuits typically involves the evaluation of important parameters at various functional levels under differing operating conditions, such as temperature. For example, the overall operation of the chip may be tested in addition to the specific testing of particularly critical circuits or circuit blocks. This is especially important with respects to complex integrated circuits where the overall device functionality may fall within specifications but the functioning of one or more internal circuit blocks is nonetheless only marginal.
The actual implementation of an efficient test protocol for a given chip is a non-trivial task subject to many variables. Among other things, if on-chip test circuitry is to be used, that test circuitry must be non-invasive. In other words, the operation of the test circuitry should not in itself alter any of the critical operating parameters of the device or disturb a critical signal path. Additionally, depending on packaging limitations, it is not always practical to provide sufficient pins for observing all the internal circuits requiring test. Further, notwithstanding the problem of access, some means must be provided to trigger the internal circuitry test mode. Finally, but of no less importance, some decision must be made as to which parameters and nodes are to be tested.
Given the importance of testing at various functional levels of an integrated circuit, improved testing techniques are required. These techniques should be non-invasive, neither disturbing critical signal paths nor dictating undue changes in the physical configuration device or packaging. They should be flexibly amenable to the testing of various internal nodes on the integrated circuit in a cost- and time-efficient fashion.